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PROGRAM

The SPI program is available here.

Sponsor Information may be further updated. The program of the IBIS meeting will be added when available.

Instructions for presenters (oral and poster) are available here.

SPI2019 HIGHLIGHTS

Tutorials - Tuesday, June 18th 2019 13:50-17:50

                                                                                                                 

Abstract. The emergence of connected smart vehicles has fully transformed the in-vehicle experience, connecting drivers and technology, and will revolutionize the future of mobility. In this tutorial, we will discuss the latest trend in IoT automotive applications and the associated SoC+platform Signal Integrity (SI) & Power Integrity (PI) design challenges. Based on the desired level of vehicle autonomy and criticality of specific design features, electronics in the vehicle are categorized into different classifications/grades (AEC, ASIL, etc.) relative to capabilities, limitations, and functional safety. The end product dictates the use conditions that the vehicle’s electronics must adhere to, including manufacturing, testing, thermal, and reliability. These use conditions can be much more stringent than standard consumer products and require diligent SI/PI engineering to work around these design challenges. At the same time, SI and PI performance enablers are in direct opposition to one another, so it becomes necessary to balance both disciplines and view the total system holistically to provide the best possible system performance. Examples of SI/PI challenges, tradeoffs, compromises, and simulation results will be presented.

                                                                                                                                                                            

Abstract. The development of advanced driver assistance systems, especially for autonomously driving cars, demands the integration of high speed interfaces to an extent previously unknown in automotive designs. The presentation will cover the specialties for signal and power integrity in today’s automotive designs and give an overview over commonly used interfaces. One focus will also be the simulation sign-off of DDR4/LPDDR4/LPDDR4X interfaces which is specifically challenging due to the various constraints that are given by JEDEC, different vendors and technology.

Keynote Speech - Wednesday, June 19th 2019 9:20-10:20 

                                                                                                

Abstract. The electric (E) field analysis is of major importance, and even mandatory, for many academic or industrial topics, such as energy monitoring, high voltage device contactless diagnostics, near field antenna characterization, bioelectromagnetism, electromagnetic compatibility, human exposure, military defence… Nevertheless, the exhaustive E-field measurement can be very complex due to the environment (very confined, presence of high magnetic field, near field configuration), to its intrinsic properties (e.g. close to or over the disruptive value, exotic polarization state, ultra-short pulse) or to societal/economic constraints. This keynote is focused on electro-optical (EO) sensing probes leading to a non-invasive and vectorial characterization of the E-field in environments and conditions not suitable for classical antennas. All the relevant characteristics leading to a comprehensive E-field measurement will be firstly defined and the EO effect will be explained. Then, a comparison with other widespread techniques (classical metallic transducers, bolometer, optoelectronic antennas…) will clarify strengths and limitations of this optical technique. The core of the presentation is dedicated to the experimental assessment of the field with several examples associated to the above identified applications. Measurement from quasi-DC up to terahertz region will be presented and analysed, for fields in guided or radiated configuration. Environments such as air, biological media or plasma are considered. I will also discuss the validity and the accuracy of absolute E-field measurements, depending obviously on the probe itself but also, dramatically, on the calibration procedure.

Interactive Industry Forum - Thursday, June 20th 2019 15:50-17:50 

                                                                                                 

Abstract. In the context of digital integrated circuits development, a growing focus on package electrical modeling is observed due to increasing operating frequencies, that make the impact of short interconnections potentially critical. In addition, package technology complexity is constantly evolving. Different platforms are available, each having its modeling challenges. Ball grid array (BGA) platform is now the standard for high-end automotive digital devices thanks to layout flexibility, that allows high interconnections density and multiple devices integration. Since many variables are involved, the electrical performance becomes strongly design-dependent and difficult to predict without accurate simulations. High density represents a challenge for simulation tools, that have to mesh very small details and provide accuracy combined to reasonable hardware requirements and runtime. A key aspect of package modeling is the strong link with design flow: simulation supports all the stages from pre-layout strategy definition to final post-layout validation. Following the trend to develop silicon, package and PCB in a co-design mode, a co-simulation approach is also needed: key aspects are tools automation, models standardization, data protection, parametric analysis. The automotive market has strict requirements in terms of electromagnetic emissions, leading to increasing interest in package-level shielding and decoupling techniques. The significant current density in advanced devices also puts the focus on electromigration effects and electro-thermal interaction, promoting a multiphysics approach.

                                                                                                

Abstract. 3D Technologies appear as a road to sidestep moore’s law stagnation by providing high energy efficient vertical interconnect suitable interposer based computing system down to tight memory & logic integration . It is also suitable for heterogeneous compact integration required by smart sensors (AI). However, exploiting the third dimension raises many challenges in order to provide optimized 3D ICs, such as architecture partitioning, design methodology, technology reliability, while considering the cost of fabrication. In this talk, the speaker will present CEA-LETI’s 3D architecture design and technology roadmap and associated co-optimization platform to optimize the power, performance, area, and cost of M3D ICs. The speaker will introduce architecture breakthroughs possible thanks to High Density 3D (pitch < 1 µm) and an overview of specific 3D ICs silicon prototypes CEA-LETI is currently designing and fabricating. He will present the 3D design tool box with a special focus on the digital design methodology, including process design kit add-on for place and route within fabrication cost guidelines, as well as 3D ICs thermal, power and signal integrity verifications. An overview of the 3D technology at device level including last pure MOSFET device status and its performance at low temperatures (CoolCubeTM), will also be exposed.

Below you will find the slides of some presentations

A Novel Programmable Delay Line for VLSI Systems - A. Bal¹, J.N. Tiwari¹, J.N. Tripathi¹, R. Achar² - ¹STMicroelectronics, Greater Noida, India; ²Carleton University, Ottawa, Canada (slide)

Finite element analysis of cable shields to investigate the behavior of the transfer impedance with respect to fast transients - S. Bauer¹, C. Türk², W. Renhart¹ and O. Bíró¹ - ¹Institute of Fundamentals and Theory in Electrical Engineering, Graz, Austria; ²Ministry of Defence of Austria, Vienna, Austria (slide)

Optimization of a Miniaturized Ethernet 10 Gbits/s 8 Conductors Interconnect for Harsh Environments - Y. Boujmad¹, P. Artillan¹, C. Bermond¹, O. Gavard², M. Prudhom², F. Khalili², E. Husson-Charlet², J.-P. Barbosa² and B. Flechet¹ - ¹IMEP-LaHC, Le Bourget du Lac, France; ²Amphenol-Socapex, Thyez, France (slide)

A Review of Compact Substrate Integrated Waveguide (SIW) Interconnects and Components - M. Bozzi¹, L. Perregrini¹ and C. Tomassoni² - ¹Dept. of Electrical, Computer and Biomedical Engineering, University of Pavia, Italy; ²Department of Engineering, University of Perugia, Italy (slide)

Mode Conversion Due To Residual Via Stubs in Differential Signaling - J. Cedeno-Chaves¹, K. Scharff², A. Carmona-Cruz¹, H.-D. Bruns², R. Rimolo-Donadio¹ and C. Schuster² – ¹Department of Electronics Engineering, ITCR, Cartago, Costa Rica; ²Institut für Theoretische Elektrotechnik, TUHH, Hamburg, Germany (slide)

A Frequency-Dependent Target Impedance Method Fulfilling Both Average and Dynamic Voltage Drop Constraints - J. Chen, M. Hashimoto - Dept. Information Systems Eng., Osaka University, Japan (slide)

A Bayesian Approach to Adaptive Frequency Sampling - S. De Ridder, D. Deschrijver, D. Spina, T. Dhaene and D. V. Ginste - IDLab, Department of Information Technology, Ghent University-imec, Belgium (slide)

Study of the coupling of wide band Near Field Scan probe dedicated to the investigation of the radiated immunity of Printed Circuit Boards - A. Durier^1,2, S. Ben Dhia² and T. Dubois³ – ¹MEA- CMR, IRT Saint Exupery, Toulouse, France; ²ESE, LAAS-CNRS / INSA Toulouse, France; ³IMS Bordeaux, France (slide)

Propagation Channel in Silicon in the Sub-THz Band for MPSoCs - I. El Masri, T. Le Gouguec and P.-M. Martin - Univ Brest, Lab-STICC, Brest, France (slide)

Prediction of Frequency Dependent Shielding Behavior for Ground Via Fences in Printed Circuit Boards – T. Hillebrecht, D. Dahl and C. Schuster - Institute of Electromagnetic Theory, Hamburg University of Technology (TUHH), Hamburg, Germany (slide)

Turnkey Methodology for Characteristic Impedance Extraction of Embedded Transmission Lines - G. Houzet, P. Artillan, C. Bermond, T. Lacrevaz and B. Flechet – IMEP-LaHC, University Savoie Mont-Blanc, Le Bourget du Lac, France (slide)

A Hierarchical Approach to the Stochastic Analysis of Transmission Lines via Polynomial Chaos - P. Manfredi and R. Trinchero - Department of Electronics and Telecommunications, Politecnico di Torino, Italy (slide)

RF line impedance optimization methodology in laminate technologies - T. Monnier¹, S. Danaie² and L. Schwartz³ – ¹ADL – Silicon Packaging; FMT – ²EWS Services; Grenoble, ³BEMT R&D – Central Packaging, STMicroelectronics, Grenoble, France (slide)

Influence of Different Digital Power Supply Layout Styles on the EME of ICs with Respect to Process Variations - A. Rauchenecker and T. Ostermann - Dept. Energy Efficient Analog Circuits and Systems, Institute for Integrated Circuits, JKU University of Linz, Austria (slide)

A Method to Determine Wide Bandgap Power Devices Packaging Interconnections - L. Pace^1,2, N. Defrance², J-C. De Jaeger², A. Videt¹ and N. Idir¹ -¹Laboratory of Electrical Engineering and Power Electronics; ²IEMN, University of Lille, France (slide)

Power Delivery Network Pre-Layout Design Planning and Analysis Through Automated Scripting - C. M. Smutzer, C. K. White, C. R. Haider, and B. K. Gilbert - Mayo Clinic, Special Purpose Processor Development Group (SPPDG), Rochester, MN USA (slide)

An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO) - M. Souilem^1,4, J. N. Tripathi², W. Dghais^3,4,5 and H. Belgacem^3,4 - ¹Ecole Nationale d'Ingénieurs de Sousse, ³Institut Supérieur des Sciences Appliquées et de Technologie, Université de Sousse, Tunisia; ²STMicroelectronics Pvt. Ltd., Noida, India; ⁴Laboratory of Elec. and Microelec. Université de Monastir, Tunisia; ⁵Laboratoire d'Ingénierie des Systèmes Industriels et des Energies Renouvelables, ENSIT, Tunis (slide)

Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects - M. Suhail Illikkal¹, J. N. Tripathi², H. Shrimali¹ and R. Achar³ – ¹School of Computing and Electrical Engineering, Indian Institute of Technology Mandi, India; ²ST Microelectronics, Greater Noida, India; ³Carleton University, Ottawa, Canada (slide)

Statistical Analysis of the Efficiency of an Integrated Voltage Regulator by means of a Machine Learning Model Coupled with Kriging Regression - R. Trinchero¹, M. Larbi², M. Swaminathan² and F. G. Canavero¹ - ¹EMC Group, Department of Electronics and Telecommunications, Politecnico di Torino, Italy; ²School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA (slide)

On the Extension of the TurboMOR-RC Reduction Method to RLC Circuits - F. Bekmambetova and P. Triverio - The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Canada (slide)